Streaming Multi-port SDRAM Memory Controller IP Core Version 3.4
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Released: 13 July 2010
Revision History
Version 3.4, Issued: July 13, 2010- Added Arria II GX support
- Improved timing script
- Fixed simulation error
- Fixed bug in write port that caused BUSY to be stuck high when local port frequency is significantly lower than SDRAM frequency
- Added Cyclone IV device support
- Improved timing script
- Improved read DQS filter
- Fixed bug in GUI generation of buffer size parameters
- Improved timing script
- Renamed files that confilicted with other Microtronix IP
- Fixed bug in write port for consecutive short writes
- Added TimeQuest support
- Improved reset timing
- Fixed potential deadlock in write port
- Improved BUSY signal behavior in read and write ports
- Fixed bug in Cyclone II LAB assignment script
- Added support for Stratix III and Arria GX
- Improved timing with DLL support for Stratix II and Arria GX
- Removed extra compilation step for Cyclone III
- Added support for Mobile DDR deep power down mode
- Fixed GUI incorrectly loading DQS, ODT and Port J parameters
- Fixed GUI bug in lsp_burst_width generation
- Fixed bug with SDR read transfers
- Fixed bug with SDR script generation
- Fixed bug with read port init and address timing
- Improved flow control signalling in read and write ports
- Increase maximum number of ports to 10
- Added OpenCore Plus evaluation patch information for Quartus 7.1
- Improved DQS routing in Cyclone III and Stratix II
- Improved Stratix II data patch
- Improved DQS logic structure
- Added Cyclone III support
- Initial release
