Avalon Multi-port DDR2 Memory Controller IP Core Version 5.3

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Released: 11 February 2010

Revision History

Version 5.3, Released: Feb 11, 2010

• Added support for Cyclone IV E and Cyclone IV GX

Version 5.2.3, Released: Feb 4, 2010

• Fixed generator script error on single DQS

Version 5.2.2, Released: Jan 12, 2010

• Added missing CMD_CLK to SOPC component

Version 5.2, Released: Dec. 22, 2009

• New GUI based on Altera's latest framework
• Generation script now saves previous .sdc and .tcl files with .bak extension before overwriting
• Ports now signal waitrequest until SDRAM initialization is complete
• Added user-settable parameter to scheduler for use in custom designs
• Improved SDC constraints

Version 5.1.2, Released: Dec. 10, 2009

• Fixed burst port off-by-one error during write bursts where write is discontinuous

Version 5.1.1, Released: Apr. 16, 2009

• Improved DQS input filtering

Version 5.1, Released: Mar. 30, 2009

• Added support for TimeQuest
• Increased ports to sixteen
• Added optional command/address clock
• Improved port scheduler
• Improved datapath to increase fmax
• Improved support for multiple controllers in a single design
• Removed "streaming" port type

Version 4.1.2, Released: Oct. 31, 2008

• Fixed bug with CKE timing

Version 4.1.1, Released: Oct. 2, 2008

• Initial release supporting Cyclone III & DDR2 devices only