I2C Master-Slave-PIO IP Core

Features

I²C Master/Slave Transmitter & Receiver IP core
I²C 8-bit PIO Slave core
I²C bus transmission speeds; 100Kbps, 400Kbps & 1Mbps
Own address and general call address detection
Input clock filter
Meets Philips I2C -bus specification version 2.1
7-bits addressing format
Single byte transmit and receive buffer
Santa Cruz I²C development board (optional)
VHDL
300 LE's for Avalon M/S, 100 LE's for PIO

Overview

The Microtronix I²C Master/Slave/PIO IP Core is a complete I2C solution offering three modes of operation and support for standard I2C bus transmission speeds. The I²C Master/Slave core provide a generic memory-mapped bus interface. Also designed as an Altera SOPC Builder Ready component, it integrates easily into any SOPC Builder generated system using an Nios® II Avalon bus.
The Microtronix I²C PIO Slave core is provided as an Altera Quartus II Megafunction and integrated into the Altera MegaWizard Plug-in Manager.
The core is optimized for all Altera FPGA's, including the newest generation of Stratix, Arria, Cyclone and MAX II devices.
Sample applications for uClinux and HAL are provided for components on the I²C bus.