Camera Link IP Core

Key Features

Standard Base, Medium & Full Channel Link interfaces
Camera and Frame Grabber configurations
7:1 Serializer/Deserializer (SerDes)
Supports 8, 10, and 12-bit video resolutions
Transmission clock rates to 85 MHz.in Cyclone devices
Bi-directional serial Camera Link communication
Configuration GUI streamlines design process
Supports Cyclone, Arria & Stratix FPGA devices

Overview

The Microtronix Camera Link IP Core is designed for building vision systems incorporating Camera Link™ communication interfaces including Base, Medium & Full Channel Link configurations. The core supports camera control signals, serial communication, and video data. It is designed for building both Camera and Frame Grabber devices.

The Camera Link standard is based on Channel Link® technology developed by National Semiconductor. Channel Link uses LVDS technology for transmitting digital data using a parallel-to-serial transmitter and a serial-to parallel-receiver to transmit data at rates up to 2.38 Gbps. The base Channel Link standard uses 28 bits to represent up to 24 bits of pixel data and 3 bits for Video Sync signals. These consist of Data Valid, Frame Valid, and Line Valid bits. The data is serialized 7:1, and the four data streams and a dedicated clock are driven over five LVDS pairs. The Receiver accepts the four LVDS data streams and one LVDS clock, and then deserializes the data into 28 bits of parallel data and a clock.

The core is designed for Altera® field programmable logic devices and is supplied with an easy-to-use Quartus® SOPC Builder Ready component.

Target Applications

The Camera Link IP Core is specifically targeted at industrial video applications including; industrial vision systems, high-speed video interconnects, Camera Link frame grabber devices, interface conversion, and video processing equipment.