Hyperdrive Multi-Port DDR2 Memory Controller IP Core, PN: 6243
Microtronix • Sep 30, 2011
Download Version 3.0.1 Now →
Released: 30 September 2011
Revision History
Version 3.0.1, Issued: Sept. 30, 2011
- Fixed bug in write port caused by odd-length writes from local bus
Version 3.0, Issued: Aug 16, 2011
- Added support for Stratix IV devices
- Improved BUSY signal behaviour for better flow-control
Version 2.3, Issued: Oct. 14, 2009
- Added TimeQuest SDC support
- Added support for Arria II GX
Version: 2.2.1, Issued: Apr. 9, 2009
- GUI modified to support 200 MHz & 233 MHz.
Version: 2.2, Issued: Dec. 12, 2008
- Added support for ECC modules
Version: 2.1, Issued: Nov. 27, 2008
- Increased maximum ports to 10
Version: 2.0.4, Issued: Oct. 31, 2008
- Increased timing parameter ranges to handle higher clock speeds
Version: 2.0.3, Issued: Oct. 15, 2008
- Fixed read port occasionally capturing address when init is low
Version: 2.0.2, Issued: Oct. 9, 2008
- Fixed write port deadlock when writing odd-length bursts
Version: 2.0.1, Issued: Oct. 7, 2008
- Fixed potential race condition in write port
Version: 2.0, Issued: Sep. 3, 2008
- Added support for Stratix III and Arria GX
- Added support for Stratix II and Arria GX DLL
Version: 1.0 Build 2,
- Added OpenCore Plus evaluation patch information for Quartus 7.1
1.0 Build 1
1.0 Build 2
- Added OpenCore Plus evaluation patch information for Quartus 7.1
1.0 Build 1