Microtronix Announces New “Enhanced” Multi-port SDRAM Memory Controller IP Core

LONDON, Ontario—January 10, 2007—Microtronix® today announced the availability of the “Enhanced” Multi-port SDRAM Memory Controller IP Core V2.3, the most significant enhancement to the Microtronix IP Core for streaming audio and video data since it debuted in 2006. The latest version: doubles the number of system bus interface ports from two to four, provides support for Avalon pipelined burst cycles, and adds DDR2, Mobile DDR memory devices. The structure of the core design is optimized for speed. Memory performance is verified for 200 MHz in a Cyclone II and 267 MHz in a Stratix II device.

Designed to shorten the development process the controller simplifies the implementation of SDRAM memory systems. For example, it incorporates a layout independent DDR Round-Trip capture scheme, and a source synchronous date capture technique to ease the design process while simultaneously boosting DDR memory clock rates. Leveraging the features of the Altera Avalon bus, it supports up to four clock-independent bus master interfaces. The core utilizes an integral data cache or FIFO's to provide independent system clocking. Avalon pipelined burst, random and streaming data interfaces supports data widths up to 128-bits.

“By using the Microtronix Multi-port SDRAM Memory Controller IP Core, you can achieve Stratix performance from a lower cost Cyclone device” said Philippe Morin, VP Sales & Marketing. “Switching from the standard SOPC Builder SDRAM IP core to the enhanced Microtronix core you can increase DDR2 clocking from 167 MHz to 200 MHz in a Cyclone II device.”

Download your free 30 day trial evaluation today at: http://www.microtronix.com.

Performance Capabilities:

• Source synchronous data capture
• Up to four system bus interface ports
• Optimized for streaming video/audio data applications
• Configurable cache minimizes memory wait-states
• Avalon Pipelined and Burst Transfers
• Layout independent DDR Round-Trip capture scheme
• Multiple time domain clocking

Features

• Supports SDR, DDR, DDR2, and Mobile DDR devices
• 200 / 267 MHz DDR2 performance in Cyclone II / Stratix II
• Configurable data width (1 - 32-bits)
• Supports up to 4 system bus interfaces
• Avalon bus widths up to 128-bits
• Altera® SOPC Builder Ready
• IP functional simulations models (VHDL)
• Supported devices: Cyclone I, II, Stratix I, II, and GX
• Altera OpenCorePlus evaluation

Pricing & Availability

The Microtronix “Enhanced” Multi-port SDRAM Memory Controller IP Core is available for immediate sale through the Microtronix Web Store and through ArrowDevTools For more information, please contact sales.

About Microtronix

Since 1977, Microtronix has pioneered the X.25 protocol for the telecommunication market. Today, Microtronix continues to lead the industry in innovation with its AMA CDR, X.25/TCP Gateways, and SMDI/SIP Solutions. Microtronix is also spearheading the embedded engineering design revolution with its complete range of services from engineering design to manufacturing. Microtronix also specializes in the rapid development of Intellectual Property and embedded applications for FPGA devices.

Much has changed since 1977 but our mission to provide the same high quality embedded engineering solutions to answer today's changing market demands, using faster embedded platforms, operating systems and high-speed connectivity that support our customers' business and strategic objectives remains unchanged.

Press Contact:

Blair Bryce
Microtronix
(888) 690-0091 x297
bbryce@microtronix.com