LONDON, Ontario—Monday, September 14, 2008—Microtronix®, a leading supplier of performance memory controller intellectual property (IP) cores today announced an upgrade of their Multi-port MDDR Memory Controller IP Core
to support 200 MHz Mobile DDR (MDDR) memory devices in Cyclone II and Cyclone III devices. This upgrade represents an approximate 20% boost in system performance from the previous version enabling designer engineers to leverage the price-performance advantage of Cyclone FPGA's for high-volume, low-power and memory intensive consumer applications.
Microtronix SDRAM memory controller IP cores are targeted at high performance single and multi-port streaming data applications. To assure the highest level of performance and reliability, the IP core deliverables include full Synopsis Design Constraint support for the TimeQuest timing analyzer and IP functional simulation models.
“The Microtronix MDDR Memory Controller IP Core enables design engineers to leverage the benefits of Mobile DDR devices in next generation embedded system.” said Blair Bryce, Sales & Marketing. “For example: by switching existing design from DDR and DDR2 designs to MDDR devices they can minimize the power dissipation without sacrificing the clock speed of their memory system. They also benefit from the longer product life-cycle of MDDR devices compared with DDR and DDR2 consumer memory solutions.”
The Microtronix MDDR Memory Controller IP Core is available with either a native Read and Write bus interface or an Altera Avalon bus for incorporation into Nios II soft-core processor systems. The cores support Cyclone, Stratix and Arria FPGA devices. Customers can request a free evaluation here.
Pricing & Availability
The Microtronix MDDR Memory Controller IP Cores are available for immediate sale. Contact: sales@microtronix.com for details.
About Microtronix
Press Contact:
Blair Bryce
Microtronix
(888) 690-0091 x297
bbryce@microtronix.com