Avalon Multi-port Front End IP Core

Multi-port Front End IP Core Overview

The Microtronix Avalon Multi-port Front End (MPFE) IP Core provides a complete, easy-to-use solution for interfacing multiple Avalon Memory Masters to a single Avalon Memory Mapped Slave ports such as the Intel PSG (Altera) DDR3/DDR4 Memory Controller IP Core.

The Avalon MPFE integrates easily into any Quartus Prime Qsys project. It is designed to optimize the performance of Avalon bus based video and streaming data systems. It supports one Avalon Memory Mapped Master port and up to 26 Avalon Memory Mapped Slave ports. The MPFE supports independent clocks for each Slave and implements buffers in on-chip memory for each port to support high speed data transfer to the Avalon Master port.

The MPFE performs arbitration between the Slave ports based on 5 service request priority levels selectable in the Qsys component.

Two types of Avalon Slave ports are available:

1. The Burst Slave port supports standard Avalon burst transfers; and,
2. The Random Slave port which implements a local cache in on chip memory and can improve performance of IP components that do not support burst transfers.

Additionally, the Slave ports have data width conversion capability to interface efficiently to IP components with different data width capabilities than that of the bus Master device.

The IP is supported in both the Standard and Pro editions of Quartus.

Key Features

• Five priority levels for arbitration of port service requests
• Up to 26 Avalon Memory Mapped Slave interfaces
• User configurable cache for each Slave port
• Each Slave port can use an independent clock
• Two Avalon Slave port types: Burst Slave and Random Slave
• Configurable memory and local bus data width optimizes logic & cost
• Round-robin (dafault) and user configurable bus arbitration / prioritization schemes
• Java configuration GUI streamlines Quartus II Qsys design process
• Supports Intel PSG: MAX 10, Cyclone, Arria and Stratix device families

Target Applications

The Avalon MPFE IP Core is targeted at high performance streaming data applications including; industrial vision systems, high-speed video interconnects, automotive control systems and video processing equipment.

Deliverables

The IP is supplied as an FTP download. It includes:

• Java Configuration GUI
• TimeQuest timing analyzer Synopsis Design Constraint (SDC) file
• VHDL ModelSim library
• User documentation
• Quartus Prime application example
• Perpetual IP Core License with 1 year of updates

Avalon MPFE IP Core Evaluation License

The Avalon MPFE IP Core complete with an Altera OpenCore Plus Evaluation License is available for immediate download by completing the Request Evaluation Form or by emailing sales to request an Evaluation License or by using the Request Evaluation icon above.

License Options

Our IP Core Licenses are perpetual and do not expire. The License is available either as a Node Locked or as a multiuser Floating Server.

• A Node Locked License is tied to the NIC ID of a PC and supports a single user.
• A Floating Seat (User) Server License supports multiple users (typically 1 through 5 seats).
  For more information refer to the Intel FPGA Software Installation and Licensing document.

IP Core Download

The current release of the Avalon Multi-port Front End IP Core is available for download from the Software Updates under the RESOURCES section of our website or directly using this link.

Custom IP Core and Feature Enhancements

Microtronix welcomes customer feedback for adding additional features or for a custom release. Contact sales with your requirements.