I2C Master-Slave-PIO IP Core

Features

• I ² C Master/Slave Transmitter & Receiver IP core
• I ² C 8-bit PIO Slave core
• I ² C bus transmission speeds; 100Kbps, 400Kbps & 1Mbps
• Own address and general call address detection
• Input clock filter
• Meets Philips I2C -bus specification version 2.1
• 7-bits addressing format
• Single byte transmit and receive buffer
• Santa Cruz I ² C development board (optional)
• VHDL
• 300 LE's for Avalon M/S, 100 LE's for PIO
• IP supports: Cyclone II - V, & Arria II - 10, Stratix II - 10 and MAX 3000/7000, MAX II/10 devices

Overview

The Microtronix I ² C Master/Slave/PIO IP Core is a complete I2C solution offering three modes of operation and support for standard I2C bus transmission speeds. The I ² C Master/Slave core provide a generic memory-mapped bus interface.

The Master and Slave IP Cores are designed as an Altera Qsys II components for integration into a Qsys generated system using an Nios® II Avalon bus.

The I ² C PIO Slave IP Core component is provided as an Altera Quartus II Megafunction and integrated into the Altera MegaWizard Plug-in Manager.

The core is optimized for all Altera FPGA's, including the newest generation of MAX, Cyclone Arria and Stratix devices.

Other Features

• Encrypted source code
• Linux Master driver
• ModelSim Test Bench
• Includes perpetual IP Core license and 1 year of maintenance updates
• 1-Hour of Installation Support

IP Core License Options

The IP is licensed for a single or for multiple FPGA device families. The base price (PN: 6232-00-01) is for a Node Locked License with support for the Cyclone device family only.

The License types include:

• Node Locked: Supports a single user. It is tied to the NIC ID of a PC.
• Floating Server: Supports multiple network users, typically 1, 2 or 5 seats.
• Source Code: VHDL or SystemVerilog

IP Core Downloads

The current release of the I ² C Master/Slave/PIO IP Core is available for download from the Software Updates support area of our website or directly using this link.