Lancero - JPEG-LS Lossless Image Encoder IP Core

The Lancero JPEG-LS Lossless Image Encoder IP Core is a highly efficient FPGA based implementation of the ITU T.87 lossless image compression standard. JPEG-LS performs better than JPEG-2000 in most lossless use cases but with less resource requirements and no need for external memory. Encoding requires less than one line of latency.

Key Features

• Leading lossless image compression results for 8 to 16 bits image sample depths
• Less than one line of encoding latency
• Low resource count, no external memory needed. Scales to multiple instances is easy
• Pixel and data FIFO input/output or Avalon Streaming interface with back-pressure
• Accepts and encodes one pixel per clock cycle
• Configurable output data word width
• Configurable image sizes up to ultra-high definition and beyond

Advanced Performance Architecture

• A 12-bit image Ultra High Definition encoder in Arria V requires 4000 ALMs and 9 M20K blocks and runs at 100 Mpixels/s
• Data reduction of photographic images by 50% to 70%

Applications

• Medical (DICOM), military, space imaging
• Surveillance camera’s
• High-end film and photo scanners
• Satellite and space imaging

Deliverables

• Encrypted Lancero JPEG-LS IP Core with pixel FIFO interface
• Altera Avalon Streaming bus wrapper
• Simulation Test Benches
• C bitstream identical model with cross validation against RTL
• Technical support
• Full SystemVerilog RTL source code can be licensed on request

Supported Devices

• Altera: Cyclone, Arria, Stratix and Hardcopy
• Xilinx: Kenex, Virtex and Ultrascale

IP Core License Options

• Node Locked: Supports a single user. It is tied to the NIC ID of a PC.
• Floating Server: Supports multiple users, typically 2 or 5 seats