Streaming Multi-port SDRAM Memory Controller IP Core

Features

• 200/333 MHz (400/666 Mbps) Cyclone / Stratix memory performance
• SDR, DDR, DDR2 and Mobile DDR SDRAM memory devices
• Up to 10 native RD or WR ports
• Memory data width: 8/16/32/64-bit
• Local bus width from 8 to 128-bits
• Configurable FIFO depth: 16 to 2048 bytes
• Intelligent SDRAM burst caching minimizes wait-states
• Layout independent DDR/DDR2 Round-Trip capture scheme
• Requires only single PLL with 4 clock outputs
• Multiple time domain clocking
• Configuration GUI streamlines design process
• Supports Cyclone II, III, IV-E, IV-GX, Stratix II, II-GX, III and Arria GX/II-GX

Memory Performance Chart

Overview

The Microtronix Streaming Multi-port SDRAM Memory Controller IP Core provides a native RD or WR local port bus interface to SDRAM memory. The core integrates: a burst memory controller core, a port arbitrator and intelligent look-ahead FIFO controller into one easy-to-use core. It supports SDR, DDR, DDR2 and Mobile DDR memory devices in a single IP Core assuring designers of a smooth low-risk migration path with changing SDRAM technology.

The core supports up to ten independently clocked streaming data sources operating from one shared high-bandwidth memory system. Using the intuitive Microtronix GUI interface, with a few clicks of a mouse, designers can create a multi-port system, a design task which would normally take several man-months of effort!

Target Applications

The core is targeted at applications requiring high bandwidth/performance memory subsystems including; HDTV consumer electronics, video conversion / enhancement equipment, military vision systems, medical imaging, data networking, Ethernet, PCIe, data recorders.

Advanced Performance Architecture

• MegaWizzard GUI for ease of configuration
• DQS data capture clocking simplifies MDDR/DDR/DDR2 PCB design constraints
• Configurable FIFO optimizes streaming video applications
• Configurable memory and local bus data width
• Independent time domain clocking optimizes memory bandwidth
• Synopsis TimeQuest support ensures timing closure*

*NOTE: Except for SDR memory devices

The Streaming Memory Controller core uses a proprietary source-synchronous clocking technology to capture DDR2 data independently from each memory device. Since data capture is no longer dependent on a common PLL system clock, timing margins are relaxed across the memory interface increasing performance by 20% or more.

This data capture technique, not only removes one PLL, it eliminates the data round-trip dependent time constraints freeing the memory design task from PCB layout parameters. By using the DQS from each memory, it removes the constraints of devices-to-device timing skews, eliminates the effects of PCB trace length variations between chips and the impact of DQS jitter and clock buffer delays. With the application of source-synchronous clocking to memory design, Microtronix has greatly lowered the barriers to building high performance wide data bus memory systems.

Other Features

• Includes easy to use configuration GUI
• VHDL IP functional simulations models
• On Die Termination (ODT) improves signal integrity
• IP Core License includes 1 year of updates
• Altera OpenCore Plus evaluation
• An optional Altera Hardcopy License is available

Note: The IP Core can be easily customized for additional bus ports or for wider data widths.

Custom cores are available

For additional information, please contact sales with your requirements.