Avalon Multi-port DDR2 Memory Controller IP Core, PN: 5240

Download Version 5.12 Now →

Released: August 18, 2014

Revision History

Version 5.12, Released: August 18, 2014

• Add support for Quartus 14
• Remove SOPC support

Version 5.7.1, Released: June 8, 2012

• Invalidate random port buffer when flush is signaled

Version 5.7, Released: April 9, 2012

• Added support for MDDR 3/4 and 1/4 memory drive strength
• Removed redundant tCK entry in GUI (this is covered by memory frequency entry)

Version 5.6, Released: Jan. 31, 2012

• Added option for ports to have double the standard width
• Added option for Random Ports to have a mechanism for forced buffer flushing through a new control port

Version 5.5.2, Released: Jan. 18, 2012

• Fixed a bug in burst port that could cause a deadlock when using the smallest buffer size.

Version 5.5.1, Released: Dec. 20, 2011

• Fixed bug in burst port that could cause incorrect data to be written if an Avalon write was initiated prior to the first waitrequest being deasserted after memory initialization.

Version 5.5, Released: August 2, 2011

• Added support for Qsys

Version 5.4.1, Issued: March 25, 2011

• Fixed bug in hw.tcl script that could cause data corruption from a burst port when connected to a narrower master that requests a large number of pipelined read transfers over a short period of time
• Improved SDC constraints

Version 5.3, Released: Feb 11, 2010

• Added support for Cyclone IV E and Cyclone IV GX

Version 5.2.3, Released: Feb 4, 2010

• Fixed generator script error on single DQS

Version 5.2.2, Released: Jan 12, 2010

• Added missing CMD_CLK to SOPC component

Version 5.2, Released: Dec. 22, 2009

• New GUI based on Altera's latest framework
• Generation script now saves previous .sdc and .tcl files with .bak extension before overwriting
• Ports now signal waitrequest until SDRAM initialization is complete
• Added user-settable parameter to scheduler for use in custom designs
• Improved SDC constraints

Version 5.1.2, Released: Dec. 10, 2009

• Fixed burst port off-by-one error during write bursts where write is discontinuous

Version 5.1.1, Released: Apr. 16, 2009

• Improved DQS input filtering

Version 5.1, Released: Mar. 30, 2009

• Added support for TimeQuest
• Increased ports to sixteen
• Added optional command/address clock
• Improved port scheduler
• Improved datapath to increase fmax
• Improved support for multiple controllers in a single design
• Removed "streaming" port type

Version 4.1.2, Released: Oct. 31, 2008

• Fixed bug with CKE timing

Version 4.1.1, Released: Oct. 2, 2008

• Initial release supporting Cyclone III & DDR2 devices only