Avalon Multi-port DDR2 Memory Controller IP Core, PN: 5240

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Released: August 18, 2014

Revision History

• Add support for Quartus 14
• Remove SOPC support

• Invalidate random port buffer when flush is signaled

• Added support for MDDR 3/4 and 1/4 memory drive strength
• Removed redundant tCK entry in GUI (this is covered by memory frequency entry)

• Added option for ports to have double the standard width
• Added option for Random Ports to have a mechanism for forced buffer flushing through a new control port

• Fixed a bug in burst port that could cause a deadlock when using the smallest buffer size.

• Fixed bug in burst port that could cause incorrect data to be written if an Avalon write was initiated prior to the first waitrequest being deasserted after memory initialization.

• Added support for Qsys

• Fixed bug in hw.tcl script that could cause data corruption from a burst port when connected to a narrower master that requests a large number of pipelined read transfers over a short period of time
• Improved SDC constraints

• Added support for Cyclone IV E and Cyclone IV GX

• Fixed generator script error on single DQS

• Added missing CMD_CLK to SOPC component

• New GUI based on Altera's latest framework
• Generation script now saves previous .sdc and .tcl files with .bak extension before overwriting
• Ports now signal waitrequest until SDRAM initialization is complete
• Added user-settable parameter to scheduler for use in custom designs
• Improved SDC constraints

• Fixed burst port off-by-one error during write bursts where write is discontinuous

• Improved DQS input filtering

• Added support for TimeQuest
• Increased ports to sixteen
• Added optional command/address clock
• Improved port scheduler
• Improved datapath to increase fmax
• Improved support for multiple controllers in a single design
• Removed "streaming" port type

• Fixed bug with CKE timing

• Initial release supporting Cyclone III & DDR2 devices only