Avalon Multi-port SDRAM Memory Controller IP Core, PN: 6240

Microtronix • August 15, 2019

Download Version 5.21 Now→

Release Date: August 15, 2019

IP Core Revision History:

Version 5.21, Issued: August 15, 2019

  • Fix an issue with the deep power down inteface not exported.
  • Add GUI configuration tabs to specify custom pin names and the clock names.
  • Disable Cyclone V delay assignments.
  • Change the DQS path for Cyclone V.
  • Fix some register power up level warning messages.

Version 5.20, Issued: March 20, 2019

  • Added support for Qsys simulation model generation

Version 5.17, Issued: May 19, 2017

  • Added MDDR, DDR & DR2 support for Cyclone 10 LP

Version 5.15, Issued: February 3, 2017

  • Changes to support Quartus versions 16.0 & 16.1

Version 5.14, Issued: January 26, 2017

  • Add simulation library support for the Cyclone V

Version 5.13, Issued: December 14, 2015

  • Add support for SDR memory on the MAX 10 device family

Version 5.12, Issued: August 18, 2014

  • Made the DQ delay chain length a GUI parameter
  • Support for quartus 14.

Version 5.11, Issued: June 30, 2014

  • Resolved a problem with DQS input clocks on Cyclone V that caused the Controller to stall on reads
Version 5.10, Issued: Match 17, 2014
  • Added constraint file generation and changed clocking recommendations for single data rate SDRAM
Version 5.9, Issued: August 16, 2013
  • Added support for Cyclone V devices
Version 5.8, Issued: August 1, 2013
  • Added support for Stratix IV devices
Version 5.7.1, Issued: June 8, 2012
  • Invalidate random port buffer when flush is signaled
Version 5.7, Issued: April 9, 2012
  • Added support for MDDR 3/4 and 1/4 memory drive strength
  • Removed redundant tCK entry in GUI (this is covered by memory frequency entry)
Version 5.6, Issued: January 31, 2012
  • Added option for ports to have double the standard width
  • Added option for Random Ports to have a mechanism for forced buffer flushing through a new control port
Version 5.5.2, Issued: January 18, 2012
  • Fixed a bug in burst port that could cause a deadlock when using the smallest buffer size.
Version 5.5.1, Issued: December 20, 2011
  • Fixed bug in burst port that could cause incorrect data to be written if an Avalon write was initiated prior to the first waitrequest being deasserted after memory initialization.
Version 5.5, Issued: July 25, 2011
  • Added support for Qsys
Version 5.4.1, Issued: March 25, 2011
  • Fixed bug in hw.tcl script that could cause data corruption from a burst port when connected to a narrower master that requests a large number of pipelined read transfers over a short period of time
  • Improved SDC constraints
Version: 5.4, Issued: July 9, 2010
  • Added support for Arria II GX
  • Fixed bug in DDR generator script
  • Fixed bug in generator script for Stratix II
Version: 5.3.2, Issued: Apr. 5, 2010
  • Updated generation of read latency value for SDR
Version: 5.3.1, Issued: Mar. 26, 2010
  • Moved execution of Quartus settings script to hw.tcl
  • Fixed bugs in generation script for SDR
Version: 5.3, Issued: Feb. 11, 2010
  • Added support for Cyclone IV E and Cyclone IV GX
Version: 5.2.3, Issued: Feb. 4, 2010
  • Fixed generator script error on single DQS
Version: 5.2.2, Issued: Jan. 12, 2010
  • Added missing CMD_CLK to SOPC component
Version: 5.2.1, Issued: Dec. 22, 2009
  • Fixed bug in Mobile DDR generator script
Version: 5.2, Issued: Dec. 10, 2009
  • New faster GUI based on Altera's latest framework in Quartus 9.1
  • Generation script now saves previous .sdc and .tcl files with .bak extension before overwriting
  • Ports now signal waitrequest until SDRAM initialization is complete
  • Added user-settable parameter to scheduler for use in custom designs
  • Added setting to support small HardCopy 2/3 devices without DDR blocks
  • Improved SDC constraints
  • Fixed bug in SDR reads
Version 5.1.2, Issued: August 28, 2009
  • Fixed burst port off-by-one error during write bursts where write is discontinuous
Version: 5.1.1, Issued: June 8, 2009
  • Improved DQS input filtering
Version: 5.1, Issued: April 16, 2009
  • Added support for TimeQuest support for DDR2 devices
  • Increased ports to sixteen
  • Added optional command/address clock
  • Improved port scheduler
  • Improved datapath to increase fmax
  • Improved support for multiple controllers in a single design
  • Removed "streaming" port type
Version: 4.1.5, Issued: Dec. 22, 2008
  • Fixed bug in Cyclone II LAB assignment script
Version: 4.1.4, Issued: Nov. 26, 2008
  • Increased timing counter widths to support higher clock frequencies
Version: 4.1.3, Issued: Nov. 7, 2008
  • Updated installer for Quartus II 8.1
Version: 4.1.2, Issued: Oct. 30, 2008
  • Fixed bug with CKE timing
Version: 4.1.1, Issued: Sep. 29, 2008
  • Initial release supporting Cyclone III & DDR2 devices only
Version: 4.1, Issued: Sep. 2, 2008
  • Added support for Arria GX
  • Added support for DLL in Stratix II and Arria GX
  • Removed extra compilation stage for Cyclone III and Stratix II
Version: 4.0, Issued: Aug. 25, 2008
  • Added support for Stratix III
Version: 3.3.1, Issued: Jun. 2, 2008
  • Improved resource utilization of random port type
Version: 3.3, Issued: May 5, 2008
  • Added support for Mobile DDR deep power down mode
  • Added option to disable automatic tcl script execution
Version: 3.2.2, Issued: Dec. 11, 2007
  • Fixed bug with short unaligned DDR2 writes
Version: 3.2.1, Issued: Nov. 21, 2007
  • Fixed bug with multiple consecutive pipelined reads of full buffer size
  • New version numbering scheme
Version: 3.2 Build 3, Issued: Sep. 27, 2007
  • Added synchronous reset
  • Added support for unaligned DDR2 transfers
  • Added support for custom scheduling algorithms, see scheduler manual
  • Fixed burst port bug
Version: 3.2 Build 2, Issued: Sep. 18, 2007
  • Fixed bug with bursts crossing page boundaries in SDRAM
Version: 3.2 Build 1, Issued: Sep. 13, 2007
  • Added fifth port option
  • Added sixth port option
Version: 3.1 Build 4, Issued: Aug. 8, 2007
  • OpenCore Plus eval working again with Altera's Quartus II 7.1SP1 Patch 1.13
Version: 3.1 Build 4
  • Fixed bug causing code download problems with SDR on Nios II
3.1 Build 2
  • Fixed bug with bursts of length (buffer+1)
3.1 Build 1
  • Added clock pairs option
  • Improved Stratix II data path
  • Improved DQS logic structure
3.0 Build 1
  • Added Cyclone III support
  • Added cache disable option
2.8 Build 1
  • Added avalon data width selection for burst port
  • Added avalon data width selection for streaming port
2.6 Build 1
  • Removed simple port type.
  • Support Quartus II / Nios II 7.0
2.5 Build 1
  • Added avalon data width selection for streaming port.
  • Added ODT support.
  • Fixed burst port datavalid/dataenable behaviour.
2.3 Build 3
  • Fixed burst port buffer error (16-word buffer)
  • Fixed burst port clocking error (very slow Avalon clock + very fast SDRAM clock)
2.3 Build 2
  • Fixed GUI parameter bug
  • Fixed minor SDR bug
2.3 Build 1
  • Added avalon burst slave
  • Added third port option
  • Added forth port
  • Added Mobile DDR support
  • Added DDR2 support
  • Fixed minor scripting bugs
1.7 Build 2
  • Fixed scripting bug
1.7 Build 1
  • Added SDRAM timing parameters tRAS and tRC
  • Added Streaming port cache release parameter
  • Added reduced drive strength option
  • Added sdram devices option
  • Improved GUI
  • Fixed minor bugs
1.3 Build 3
  • Fixed SDR scripting bug
1.3 Build 2
  • Improved performance of random and streaming port types
1.3 Build 1
  • Added dual port variable for Nios IDE
  • Added wizard finish section
  • Fixed DQ/DQS mismatch for 32-bit DDR
1.0 Build 2
  • Fixed Opencore+ timeout
1.0 Build 1
  • Initial release

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