Camera Link Aligner IP Core

Link Aligner IP Core Overview

The Microtronix Camera Link Aligner IP Core is designed for building Frame Grabber (Receiver) Medium & Full Channel Link™ interfaces in conjunction with the LVDS SerDes blocks of Intel PSG FPGA series 10-GX device families . The core includes supports for the adjunct Camera Link serial control and data communication signals.

The Link Aligner synchronizes the data between Channel Links in Medium and Full Camera Link Frame Grabber configurations. The using FIFO's the Aligner synchronizes the data across Links by removing delays caused by phase differences of the clock sources between Channel Links or cable length mismatches. The Link Aligner block compares the LVAL signal from each Channel Link and using FIFO's auto adjusts the our delays to bring the links into phase alignment. It also synchronizes data at the output Ports to the STROBE/XCLK clock.

The IP also includes a Power Over Camera Link (PoCL) SafePower logic block, which when implemented with supporting hardware, allows a Frame Grabber to provide DC power to PoCL cameras and while still remaining compatible with non-PoCL cameras. The SafePower IP block works with the PoCL circuitry on the Microtronix Camera Link Receiver HSMC Daughter Card.

Key Features

• Auto Link Aligner for 8-bit, 10-tap Base, Medium & Full Frame Grabber configurations
• Supports 64-bit and 80-bit extended Full configurations
• Pixel clock rates to 85 MHz.
• Power Over Camera Link (PoCL) SafePower
• Bi-directional serial Camera Link communication
• Java configuration GUI streamlines Quartus design process
• Leverages the LVDS SerDes blocks of Cyclone V-GX/10-GX, Arria V/10 GX, and Stratix IV/V GX devices for building Frame Grabber systems

Target Applications

The Camera Link Aligner IP Core is targeted at Frame Grabber applications including; industrial vision systems, high-speed video interconnects, video capture devices, interface conversion, and video processing equipment.

Deliverables

The IP is supplied as an FTP download. It includes:

• Java Configuration GUI
• TimeQuest timing analyzer Synopsis Design Constraint (SDC) file
• VHDL ModelSim library
• User documentation
• Quartus Reference Design supporting a Camera Link Medium & Full receiver configurations
• Perpetual IP core license with 1 year of updates

IP Core Evaluation License

A 30-day Intel PSG OpenCore Plus evaluation license available. Email sales to request an Evaluation License or use the request evaluation icon above.

License Options

The IP Core license is perpetual and does not expire. It is available either as a Node Locked or Floating Server.

• Node Locked: Supports a single user. It is tied to the NIC ID of a PC.
• Floating Server: Supports multiple users (typically 2 or 5 seats)

IP Core Downloads

The current release of the Camera Link Aligner IP Core is available for download from the Software Updates support area of our website or directly using this link.