Microtronix Announces JPEG-LS Lossless Image Encoder IP Core

LONDON, Ontario, Monday April 27, 2015 — Microtronix today announced the release of the Lancero JPEG-LS Lossless Image Encoder IP Core for Altera and Xilinx high performance FPGA devices. The core is a highly efficient implementation of the ITU T.87 Lossless Image Compression Standard which offers a 50% to 70% data reduction in the transmission of photographic images A 12-bit image 16 Megapixel (4K x 4K) encoder implemented for Arria V requires only 4000 ALMs and 9 M20K blocks (77214 bits) and runs at 100 Mpixels/second. Instantiating 16 encoders in parallel on the IP achieves 100 Mpixels per second on Arria V GZ, with 12 bits per pixel.

Functional Overview

• Leading lossless image compression results for 8 to 16 bits image sample depths.
• Less then one line of encoding latency.
• Low resource count, no external memory needed..
• Pixel and data FIFO input/output or Avalon Streaming interface with back-pressure.
• Accepts and encodes one pixel per clock cycle.
• Configurable output data word width.
• Configurable image sizes up to Ultra High Definition (8K) and beyond.

Availability

Contact Microtronix Sales today for pricing and availability or visit our website to request an Evaluation Core. Distributors & Resellers inquiries are welcomed.

About Microtronix

Microtronix is a full service product development company offering an integrated suite of hardware and software design services tailored to quickly get new products to the marketplace. For over 20 years, Microtronix has empowered customers worldwide with custom networking communications products. Today, Microtronix continues to apply their proven engineering practices and expertise in developing innovative video solutions to design cost effective embedded products, FPGA based hardware, IP cores and printed circuit boards.

Press Contact:

Norman McCall
Microtronix
(519) 690-0091 x264
nmccall@microtronix.com