Streaming Multi-port SDRAM Memory Controller IP Core, PN: 6248

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Released: 29 Oct. 2013

Revision History

Version 4.2 Issued: Oct. 29, 2013

• Added Cyclone V Support

Version 4.1 Issued: Oct. 12, 2012

• Update SDR PLL phase shift script to support TimeQuest

Version 4.0 Issued: May 22, 2012

• Add SystemVerilog language support

Version 3.5.2 Issued: March 16, 2012

• Clean up Design Assistant warnings

Version 3.5.1 Issued: December 15, 2011

• Added assertion of BUSY until memory initialization complete

Version 3.5 Issued: August 24, 2011

• Added Stratix IV support
• Improved timing constraints

Version 3.4.1, Issued: November 2, 2010

• Fixed bug in write port that that could cause missed data after a reset, when local port frequency is significantly lower than SDRAM frequency

Version 3.4, Issued: July 13, 2010

• Added Arria II GX support
• Improved timing script
• Fixed simulation error

Version 3.3.1, Issued: May 21, 2010

• Fixed bug in write port that caused BUSY to be stuck high when local port frequency is significantly lower than SDRAM frequency

Version 3.3, Issued: Feb. 8, 2010

• Added Cyclone IV device support

Version 3.2.3, Issued: Dec. 22, 2009

• Improved timing script
• Improved read DQS filter

Version 3.2.2, Issued: Sept. 29, 2009

• Fixed bug in GUI generation of buffer size parameters

Version 3.2.1, Issued: July 30, 2009

• Improved timing script
• Renamed files that confilicted with other Microtronix IP
• Fixed bug in write port for consecutive short writes

Version 3.2, Issued: July 13, 2009

• Added TimeQuest support
• Improved reset timing

Version: 3.1.1, Issued: June 1, 2009

• Fixed potential deadlock in write port

Version: 3.1, Issued: March 25, 2009

• Improved BUSY signal behavior in read and write ports

Version: 3.0.1, Issued: Jan. 6, 2009

• Fixed bug in Cyclone II LAB assignment script

Version: 3.0, Issued: Sep. 3, 2008

• Added support for Stratix III and Arria GX
• Improved timing with DLL support for Stratix II and Arria GX
• Removed extra compilation step for Cyclone III

Version: 2.1, Issued: June 2, 2008

• Added support for Mobile DDR deep power down mode
• Fixed GUI incorrectly loading DQS, ODT and Port J parameters

Version: 2.0.4, Issued: April 30, 2008

• Fixed GUI bug in lsp_burst_width generation

Version: 2.0.3, Issued: April 25, 2008

• Fixed bug with SDR read transfers

Version: 2.0.2, Issued: April 16, 2008

• Fixed bug with SDR script generation

Version: 2.1, Issued: June 2, 2008

• Fixed bug with read port init and address timing

Version 2.0, Issued: Dec. 28, 2007

• Improved flow control signalling in read and write ports

Version: 1.4 Build 1

• Increase maximum number of ports to 10

Version: 1.3 Build 2

• Added OpenCore Plus evaluation patch information for Quartus 7.1

Version: 1.3 Build 1

• Improved DQS routing in Cyclone III and Stratix II

Version: 1.2 Build 1

• Improved Stratix II data patch
• Improved DQS logic structure

Version: 1.1 Build 1

• Added Cyclone III support

Version: 1.0 Build 1

• Initial release